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Autor(en) / Beteiligte
Titel
7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET
Ist Teil von
  • 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.123-125
Ort / Verlag
IEEE
Erscheinungsjahr
2024
Quelle
IEEE
Beschreibungen/Notizen
  • The application of artificial intelligence (AI) and machine learning (ML) in network switching and cloud computing require 200Gb/s per wavelength to minimize the number of optical ports and enable a cost-effective solution to meet the higher throughput demands. In turn, this data rate requires aggressive performance metrics such as high transceiver bandwidth (BW) that is 2 times higher than the previous generation, low circuit noise, and low clock jitter. In addition, lower power consumption per bit is needed to fit into the optical module power envelop which is specified by multi-source agreements (MSA) such as OSFP-XD. This work presents a low-power and high-performance 200Gb/s transceiver used for optical direct-detect applications. Figure 7.1.1 shows an example 800Gb/s optical module where the line side is made up of 4 lanes, with each lane consisting of a 200Gb/s transmitter (TX) and 200Gb/s receiver (RX). To leverage the power and area benefits in technology scaling, a digital to analog converter (DAC) based TX and an analog to digital converter (ADC) based RX running at 106GS/s are used. In the TX, an FIR filter pre-compensates for the channel BW limitation, and digital pre-distortion adjusts PAM-4 inner levels for optimal SNR performance. In the RX, the sampled ADC signal is equalized by an FFE and a reflection canceller, and depending on channel conditions, a DFE and maximum likelihood sequence detector (MLSD) can be enabled for higher SNR performance.
Sprache
Englisch
Identifikatoren
eISSN: 2376-8606
DOI: 10.1109/ISSCC49657.2024.10454275
Titel-ID: cdi_ieee_primary_10454275

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