Details

Autor(en) / Beteiligte

• Lee, Gwi-Deok Ryan
• Kim, Dae-Hoon
• Kwon, Doowon
• Park, Jong-Eun
• Cho, Dongseok
• Kang, Jeongsoon
• Park, Gyunha
• Kang, Junha
• Jang, Minho
• Oh, Seungjae
• Kim, Doyeon
• Yoon, Sol
• Kim, Yongjun
• Park, Sejin
• Lim, Kyungtae
• Oh, Dongjun
• Kang, SooYoung
• Park, Keunhyoung
• Kim, Changhwa
• Kim, Hyoju
• Kim, Taeyeong
• Lee, Kyu-Ha
• Cho, Hyoukyung
• Hwang, Son-Kwan
• Lee, Hojin
• Lee, Jae-Kyu
• Kim, Hyunchul
• Moon, Chang-Rok
• Song, Jaihyuk

Titel

A 0.5µm Pixel 3-layer Stacked CMOS Image Sensor with Deep Contact and In-pixel Cu-Cu Bonding Technology

Ist Teil von

• 2023 International Electron Devices Meeting (IEDM), 2023, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2023

Quelle

IEEE Xplore

Beschreibungen/Notizen

• 64Mp CIS with 0.5um pixels has been developed with three wafer layers (e.g. top-wafer for PDs and TG TRs, mid-wafer for pixel TRs, and bottom-wafer for the analog and logic circuits). The RTS noise was reduced by 85% compared to ones of the conventional structure with over 6,000e-FWC as similar to our previous research [1] - [3]. In addition, the FD conversion gain was improved by 67% with the Miller effect due to the reduction of the DCNT capacitance.