Details

Autor(en) / Beteiligte

• Ouyang, Siyuan
• Zhou, Keji
• Jiang, Hao
• Li, Chenyang
• Liang, Jinhao
• Zhu, Fangduo
• Zhang, Xumeng
• Liu, Qi

Titel

A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips

Ist Teil von

• IEEE transactions on circuits and systems. II, Express briefs, 2024-05, Vol.71 (5), p.2804-2808

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2024

Quelle

IEEE/IET Electronic Library (IEL)

Beschreibungen/Notizen

• In multi-core neuromorphic chips, asynchronous Address-Event-Representation (AER) circuit is commonly used to encode and transmit spikes between neurons in different cores. Existing asynchronous AER circuits using bundled data protocol are mainly constructed in pipelined tree structure. The delay and area of these circuits increase significantly as the input channel number increases. This brief proposes a new AER unit using mask-based arbitration scheme, which is able to significantly reduce the area and delay for sparse event at the cost of high power consumption and low throughput. A dual-level mask AER structure is proposed to mitigate the drawbacks. According to the simulation result, the dual-level mask AER has a reduction of 48% in area and 17%-39% in delay with respect to pipelined tree AER, while the power consumption increasement is no more than 19% of pipelined tree. What's more, the dual-level scheme exhibits competitive performance in delay when compared to the delay-insensitive AER schemes.