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A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3
Ist Teil von
2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-3
Ort / Verlag
IEEE
Erscheinungsjahr
2023
Quelle
IEEE Electronic Library Online
Beschreibungen/Notizen
As the demand for high-performance computers and systems including machine learning increases, high-bandwidth memory (HBM) is preferred due to its large capacity, low power consumption, and high bandwidth. The latest HBM3 standard supports a 6.4 Gbps transmission speed per PIN and a total of 1024 10 PINs are used to support a total data rate of up to 819 GB/s. The high data rate and a lot of IOs inevitably increase the power consumption in the 10 circuit which increases the internal power supply noise. Since this power noise is converted into power supply induced jitter (PSIJ) in the clock buffer circuit and decrease the 10 timing margin, a method to reduce PSIJ for high data rates effectively is required. Conventionally, a decoupling capacitor is used to reduce power noise. And as shown in Fig. 1 (top), HBM uses the cell-capacitors in the core-die as a decoupling capacitor across the through-silicon-via (TSV) because of lack of the area in the buffer-die (B-die). However, the stacked core-dies increase the equivalent series resistor (ESR), which is composed of RTSV and Rrouting. The increased ESR induces the power noise, as shown in Fig. 1 (bottom-left), and makes worsen PSIJ. To isolate the power supply noise, LDO can be applied in HBM3 for the DQS buffer. However, several operating modes with different current profile in HBM impose several critical constraints on the LDO. In this paper, we propose the compact ultra-high speed LDO that specialized in the DRAM structure with several operation modes with active inductor, self-adaptive bias and 2-step technique.