Details

Autor(en) / Beteiligte

• Jeon, Hojin
• Park, Jeeyeon
• Byeon, Kiryun
• Jung, Jiho
• Kim, Hongjin

Titel

A 3V 12Bit 4MS/s Asynchronous SAR ADC with On-Chip 3-Step Background Calibration Using Split Structure

Ist Teil von

• 2023 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC), 2023, p.1-6

Ort / Verlag

IEEE

Erscheinungsjahr

2023

Quelle

IEEE Explore

Beschreibungen/Notizen

• This paper presents an energy-efficient 12-bit successive approximation register analog-digital converter for 3-step calibration. This 3-step background calibration works only once during initial start-up to calibration capacitor mismatch, offset, and logic delay. Through this calibration, it was possible to have high linearity and a small offset error in a small area. After calibration, the SNDR improved from 55 dB to 69 dB at 4MS/s, and the offset error also improved by 2 mV from 20 mV. The Optimal effective number of bits is 11.2bit at the Nyquist-rate input, which is equivalent to a figure of merit of 167.23dB.