Details

Autor(en) / Beteiligte

• Srbljanovic, Aleksa
• Rikalo, Aleskandar
• Dodovic, Matija
• Stojanovic, Sasa
• Micovic, Marko

Titel

Implementation of a unified modern interface for executing hardware simulation, synthesis, and verification processes of VLSI systems

Ist Teil von

• 2023 10th International Conference on Electrical, Electronic and Computing Engineering (IcETRAN), 2023, p.1-5

Ort / Verlag

IEEE

Erscheinungsjahr

2023

Link zum Volltext

Quelle

IEEE Xplore Digital Library

Beschreibungen/Notizen

• The course Computer systems for VLSI, held in the fourth year of undergraduate studies at the School of Electrical Engineering, University of Belgrade, introduces students to the Verilog and SystemVerilog languages and the processes of device simulation, synthesis, and verification. As the course covers a large number of new concepts in the field of VLSI systems, practical classes cover several Integrated Development Environments that students first need to become familiar with. However, the tools used in this area have not been modernized, which further complicates their use. This paper presents the advantages and disadvantages of the existing environment and proposes the implementation of a new, unified and modern interface for executing device simulation, synthesis, and verification processes.