Details

Autor(en) / Beteiligte

• Jo, Youngmin
• Kavala, Anil
• Kim, Tongsung
• Chun, Byungkwan
• Park, Jung-June
• Lee, Taesung
• Seo, Jungmin
• Yang, Manjae
• Park, Taehyeon
• Kwon, Hyunjin
• Lee, Cheolhui
• Son, Younghoon
• Kwak, Junghwan
• Lee, Younggyu
• Ku, Hwan Seok
• Na, Daehoon
• Yu, Changyeon
• Park, Jonghoon
• Kim, JaeHwan
• Kwon, Hyojin
• Kim, Chanho
• Jung, Moon-Ki
• Park, Chanjin
• Seo, Donghyun
• Kim, Moosung
• Lee, Seungjae
• Lee, Jin-Yub
• Kang, Dongku
• Yoon, Chiweon
• Hur, SungHoi

Titel

A 3.0 Gb/s/pin 4th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package

Ist Teil von

• 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

Ort / Verlag

JSAP

Erscheinungsjahr

2023

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A 1.2 V, 3.0 Gb/s/pin 16Tb NAND flash memory package with proposed 4 th generation F-chip is presented. It is implemented with self-training techniques such as hybrid delay locked loop (DLL) and 3-step duty cycle correction (DCC) to overcome the speed bottlenecks in F-chip to NAND interface. Also, its multi-termination feature improves power efficiency by providing the use of different terminations on its interfaces. This work achieves an I/O speed of 3.0 Gb/s and power consumption of 58mW which are an improvement of 66% and 23.3%, respectively, in comparison with 3 rd generation F-chip.