Details

Autor(en) / Beteiligte

• Han, J.W.
• Park, S.H.
• Jeong, M.Y.
• Lee, K.S.
• Kim, K.N.
• Kim, H.J.
• Shin, J.C.
• Park, S.M.
• Shin, S.H.
• Park, S.W.
• Lee, J.H.
• Kim, S.H.
• Kim, B.C
• Jung, M.H.
• Yoon, I.Y.
• Kim, H.
• Jang, S.U.
• Park, K.J.
• Kim, Y.K.
• Kim, I.G.
• Oh, J.H
• Han, S.Y.
• Kim, B.S.
• Kuh, B.J.
• Park, J.M.

Titel

Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM

Ist Teil von

• 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

Ort / Verlag

JSAP

Erscheinungsjahr

2023

Quelle

IEL

Beschreibungen/Notizen

• For the past decades, the density of DRAM has been remarkably increased by making access transistors and capacitors smaller in size per unit area. However, shrinking devices far beyond the 10 nm process node increasingly poses process and reliability challenges. As Flash technology made a pivotal and successful innovation via 3D NAND, DRAM technology may also adopt vertical stacking memory cells. Vertically stacked DRAM (VS-DRAM) continues to increase bit density on a die by increasing the number of layers along with reducing the size of the transistor. In this paper, the opportunities and challenges of VS-DRAM are discussed.