Details

Autor(en) / Beteiligte

• Tan, Fei
• Yu, Wei-Han
• Un, Ka-Fai
• Martins, Rui P.
• Mak, Pui-In

Titel

A 0.05- ^ 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS

Ist Teil von

• IEEE journal of solid-state circuits, 2023-07, p.1-10

Ort / Verlag

IEEE

Erscheinungsjahr

2023

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• This article reports a keyword-spotting (KWS) chip for voice-controlled devices. It features a number of techniques to enhance the performance, area, and power efficiencies: 1) a fast-sampling convolutional neural network (FS-CNN) that eliminates the power-hungry feature extractors and reduces the decision latency; 2) an always-retention 5T-SRAM that features word-voltage switches to reduce the leakage power and single bitline (BL) operation to halve the SRAM read power compared to the typical 6T-SRAM; and 3) a high-resolution sparsity-aware computing (HR-SAC) unit that enhances the precision and output swing of the multiply-accumulate (MAC) computation. Benchmarking with the state-of-the-art, our KWS chip prototyped in 28-nm CMOS scores a <inline-formula> <tex-math notation="LaTeX">></tex-math> </inline-formula>90% accuracy for the 11-class Google speech command dataset (GSCD) at 2.91 <inline-formula> <tex-math notation="LaTeX">\mu</tex-math> </inline-formula>W, which corresponds to a 2.91-nJ energy/decision. The achieved latency is 2 ms/decision, and the core area is 0.05 <inline-formula> <tex-math notation="LaTeX">{\rm mm}^{2}</tex-math> </inline-formula>, including the full KWS model.