Details

Autor(en) / Beteiligte

• Hyunpil Noh
• Suock Jeong
• Seongjoon Lee
• Yousung Kim
• Woncheol Cho
• Min Huh
• Gucheol Jeong
• Jaebuhm Suh
• Hoyeop Kweon
• Jaesung Roh
• Kisoo Shin
• Sangdon Lee

Titel

A 0.08 /spl mu/m/sup 2/-sized 8F/sup 2/ stack DRAM cell for multi-gigabit DRAM

Ist Teil von

• 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303), 2002, p.56-57

Ort / Verlag

IEEE

Erscheinungsjahr

2002

Quelle

IEEE Xplore / Electronic Library Online (IEL)

Beschreibungen/Notizen

• The first 8F/sup 2/ stack DRAM cell with 0.08 /spl mu/m/sup 2/ size has been successfully integrated by employing a poly plug scheme for landing plug contacts and W/poly gates and Ru MIM capacitors, of which cell working has been proven under easy function check mode. The cell transistor with W gate technology exhibits sufficient saturation current (I/sub OP/) of /spl sim/40 /spl mu/A with threshold voltage (V/sub tsat/) of 0.9 V and satisfactory ring oscillator delay characteristics of /spl sim/50 ps.