Details

Autor(en) / Beteiligte

• Khakifirooz, Ali
• Anaya, Eduardo
• Balasubrahmanyam, Sriram
• Bennett, Geoff
• Castro, Daniel
• Egler, John
• Fan, Kuangchan
• Ferdous, Rifat
• Ganapathi, Kartik
• Guzman, Omar
• Ha, Chang Wan
• Haque, Rezaul
• Harish, Vinaya
• Jalalifar, Majid
• Jungroth, Owen W.
• Kang, Sung-Taeg
• Karbasian, Golnaz
• Kim, Jee-Yeon
• Li, Siyue
• Madraswala, Aliasgar S.
• Maddukuri, Srivijay
• Mohammed, Amr
• Mookiah, Shanmathi
• Nagabhushan, Shashi
• Ngo, Binh
• Patel, Deep
• Poosarla, Sai Kumar
• Prabhu, Naveen V.
• Quiroga, Carlos
• Rajwade, Shantanu
• Rahman, Ahsanur
• Shah, Jalpa
• Shenoy, Rohit S.
• Menson, Ebenezer Tachie
• Tankasala, Archana
• Thirumala, Sandeep Krishna
• Upadhyay, Sagar
• Upadhyayula, Krishnasree
• Velasco, Ashley
• Vemula, Nanda Kishore Babu
• Venkataramaiah, Bhaskar
• Zhou, Jiantao
• Pathak, Bharat M.
• Kalavade, Pranav

Titel

A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3 Gb/mm2 Bit Density

Ist Teil von

• IEEE solid-state circuits letters, 2023-06, Vol.6, p.1-1

Ort / Verlag

Piscataway: IEEE

Erscheinungsjahr

2023

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• We present the industry's first 5b/cell (PLC) NAND chip, fabricated in a 192-layer floating-gate (FG) technology. With a die capacity of 1.67 Tb and an area of 73.3 mm2, it delivers a record bit density of 23.3 Gb/mm2. Key innovations to enable reliable PLC operation and the features implemented to support system-level usage are described. These include: a fast soft-bit read algorithm capable of handling the presence of defective bitlines; a fast read-calibration algorithm; a reverse-read waveform to improve the read margin; SLC-write-through; and program suspend and resume algorithm compatible with the above read operations.