IEEE transactions on signal processing, 2002-07, Vol.50 (7), p.1772-1779
2002
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Details
- Autor(en) / Beteiligte
- Titel
- Adder based residue to binary number converters for (2/sup n/-1, 2/sup n/, 2/sup n/+1)
- Ist Teil von
- IEEE transactions on signal processing, 2002-07, Vol.50 (7), p.1772-1779
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2002
- Quelle
- IEEE Electronic Library Online
- Beschreibungen/Notizen
- Based on an algorithm derived from the new Chinese remainder theorem I, we present three new residue-to-binary converters for the residue number system (2/sup n/-1, 2/sup n/, 2/sup n/+1) designed using 2n-bit or n-bit adders with improvements on speed, area, or dynamic range compared with various previous converters. The 2n-bit adder based converter is faster and requires about half the hardware required by previous methods. For n-bit adder-based implementations, one new converter is twice as fast as the previous method using a similar amount of hardware, whereas another new converter achieves improvement in either speed, area, or dynamic range compared with previous converters.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 1053-587XeISSN: 1941-0476DOI: 10.1109/TSP.2002.1011216Titel-ID: cdi_ieee_primary_1011216
- Format
- –
- Schlagworte
- Adders, Algorithm design and analysis, Applied sciences, Arithmetic, Cathode ray tubes, Circuit properties, Computer science, Detection, estimation, filtering, equalization, prediction, Digital signal processing, Dynamic range, Electric, optical and optoelectronic circuits, Electronic circuits, Electronics, Exact sciences and technology, Hardware, Information, signal and communications theory, Signal and communications theory, Signal convertors, Signal processing algorithms, Signal, noise, Telecommunications and information theory, Very large scale integration