Details

Autor(en) / Beteiligte

• Qiu, Junjun
• Wang, Wenqian
• Sun, Zheng
• Liu, Bangan
• Zhang, Yuncheng
• Xu, Dingxin
• Huang, Hongye
• Fadila, Ashbir Aviat
• Liu, Zezheng
• Madany, Waleed
• Xiong, Yuang
• Shirane, Atsushi
• Okada, Kenichi

Titel

A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration

Ist Teil von

• 2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.80-82

Ort / Verlag

IEEE

Erscheinungsjahr

2023

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A 32.768kHz-reference (REF) phase-locked loop (PLL) can help eliminate the high-frequency crystal oscillator in a wireless system-on-chip (SoC), which would significantly reduce the cost and improve power efficiency [1-3]. With the conventional 1{\times}-\text{sampling} PLL, the loop bandwidth of the PLL is limited to 1/10 of the REF frequency (\mathrm{f}_{\text{REF}}) . To break the limitation of the narrow bandwidth and poor jitter caused by low \mathrm{f}_{\text{REF}} , the reference-oversampling PLL (OSPLL) was studied [3]. However, different from the high \mathrm{f}_{\text{REF}} [4], [5], the 32kHz-REF PLL severely suffers from jitter transferred from voltage noise (mainly from a comparator) from a slow signal slope, which degrades the total jitter performance. To overcome the above issues, a nonuniform OSPLL is proposed with a 32kHz REF to realize a 2.4GHz output with a fractional-N operation. The proposed DAC-and-DTC-assisted nonuniform OSPLL works with a proposed gain-boosted phase detector (PD) and an adaptive loop-gain calibration. It realizes a 200kHz loop bandwidth, 4.95ps rms jitter with 3.8mW power consumption in a 65nm CMOS technology.