Details

Autor(en) / Beteiligte

• Ker, Ming-Dou
• Hsu, Sheng-Fu

Titel

Summary

Ist Teil von

• Transient-Induced Latchup in CMOS Integrated Circuits, 2010

Ort / Verlag

John Wiley & Sons

Erscheinungsjahr

2010

Quelle

Wiley Online Library All Obooks

Beschreibungen/Notizen

• gives a brief summary of TLU. The concepts to extract compact and safe design rules for latchup or TLU prevention are also summarized. A practical example of extracting layout rules/guidelines for latchup prevention in a 0.18-µm 1.8V/3.3V silicided CMOS process is given in appendix. The methodologies to extract all the latchup design rules/guidelines are in compliance with those presented in Chapter 6, including latchup layout rules for I/O cells, for internal circuits, and for between I/O and internal circuits. Latchup layout rules for circuits across two different power domains are also extracted to avoid the possible latchup danger between two n-wells powered by two different power supply voltages, as introduced in Chapter 7. Such skills can be further implemented in any given CMOS process to extract reliable design rules without suffering latchup danger.