Details

Autor(en) / Beteiligte

• Ker, Ming-Dou
• Hsu, Sheng-Fu
• Ker, Ming‐Dou
• Hsu, Sheng‐Fu

Titel

Special Layout Issues for Latchup Prevention

Ist Teil von

• Transient-Induced Latchup in CMOS Integrated Circuits, 2010, p.151-168

Ort / Verlag

Chichester, UK: John Wiley & Sons

Erscheinungsjahr

2010

Quelle

Wiley Online Library All Obooks

Beschreibungen/Notizen

• introduces several special layout issues for latchup prevention. Neglecting these layout issues could draw the unanticipated latchup danger, including latchup between two power domains, between power-pins and grounded N+/N-well, and between two adjacent I/O cells, etc. The ESD-coupled diodes between separated power lines can also lead to the unexpected latchup. Direct connection between I/O pads and the N+/P+ diffusions in internal circuits could easily initiate latchup in internals circuits. Additionally, if the power-rail ESD clamp circuit is very close to the I/O pads, ESD-clamping NMOS could be unexpectedly turned on during the negative trigger current test, probably initiating the latchup in the nearby internal circuits. The corresponding solutions to these unexpected latchup issues are also introduced. By using these IC designers could prevent the possible design mistakes, eliminate the waste of masks and wafers, and decrease the time to market for products.