Details

Autor(en) / Beteiligte

• Hsu, Yu‐Chieh
• Chen, Yan‐Yu
• Shieh, Jia‐Min
• Huang, Wen‐Hsien
• Shen, Chang‐Hong
• Chueh, Yu‐Lun

Titel

Design on Formation of Nickel Silicide by a Low‐Temperature Pulsed Laser Annealing Method to Reduce Contact Resistance for CMOS Inverter and 6T‐SRAM on a Wafer‐Scale Flexible Substrate

Ist Teil von

• Advanced electronic materials, 2023-12, Vol.9 (12), p.n/a

Ort / Verlag

Seoul: John Wiley & Sons, Inc

Erscheinungsjahr

2023

Quelle

Wiley Online Library

Beschreibungen/Notizen

• A pulsed laser annealing method is utilized to directly synthesize nickel silicide (NiSi) as a contact material to improve the contact of electric devices. Three laser wavelengths, 355 nm (ultraviolet laser), 532 nm (green laser), and 1064 nm (infrared laser), are used for the NiSi synthesis during the pulsed laser annealing process. A NiSi phase with low sheet resistance is formed by an ultraviolet laser annealing (ULA) process without damaging the polyimide (PI) substrate. With the integration of the ULA process‐induced NiSi into p‐nnel MOSFET (PMOS) and n‐channel MOSFET (NMOS) devices, the on/off ratio improves significantly, and the field‐effect mobility increases by 30% because of the reduction in contact resistance from 21 to 8.5 kΩ. In addition to the PMOS and NMOS, the gains of the CMOS inverter at different Vdd values are improved by at least 30%. Moreover, the static noise margin of 6T‐SRAM is elevated from 0.82 to 1 V at Vdd = 4 V. The ability of the ULA process to synthesize a high‐quality NiSi layer on a flexible substrate is demonstrated. The integration of NiSi into electrical devices offers a new pathway for improving the electrical behavior of flexible devices. A pulsed laser annealing method is applied to synthesize nickel silicide (NiSi) as a contact material. With the integration of NiSi into p‐channel MOSFET and n‐channel MOSFET devices, the on/off ratio improves and the field‐effect mobility increases because of a reduction in contact resistance.. In addition, the gains of the CMOS inverter are improved and the static noise margin of 6T‐SRAM is also increased.