Details

Autor(en) / Beteiligte

• Erfani Majd, Nasser
• Fani, Rezvan

Titel

Low‐clock‐speed time‐interleaved architecture for a polar delta–sigma modulator transmitter

Ist Teil von

• ETRI journal, 2023-02, Vol.45 (1), p.150-162

Ort / Verlag

Electronics and Telecommunications Research Institute (ETRI)

Erscheinungsjahr

2023

Link zum Volltext

Quelle

EZB Electronic Journals Library

Beschreibungen/Notizen

• The polar delta–sigma modulator (DSM) transmitter architecture exhibits good coding efficiency and can be used for software‐defined radio applications. However, the necessity of high clock speed is one of the major drawbacks of using this transmitter architecture. This study proposes a low‐complexity time‐interleaved architecture for the polar DSM transmitter baseband part to reduce the clock speed requirement of the polar DSM transmitter using an upsampling technique. Simulations show that using the proposed four‐branch time‐interleaved polar DSM transmitter baseband part, the clock speed requirement of the transmitter is reduced by four times without degrading the signal‐to‐noise‐and‐distortion ratio.