Details

Autor(en) / Beteiligte

• Schöffel, Maximilian
• Lauer, Frederik
• Rheinländer, Carl C
• Wehn, Norbert

Titel

Secure IoT in the Era of Quantum Computers-Where Are the Bottlenecks?

Ist Teil von

• Sensors (Basel, Switzerland), 2022-03, Vol.22 (7), p.2484

Ort / Verlag

Switzerland: MDPI AG

Erscheinungsjahr

2022

Link zum Volltext

Quelle

Electronic Journals Library - Freely accessible e-journals

Beschreibungen/Notizen

• Recent progress in quantum computers severely endangers the security of widely used public-key cryptosystems and of all communication that relies on it. Thus, the US NIST is currently exploring new post-quantum cryptographic algorithms that are robust against quantum computers. Security is seen as one of the most critical issues of low-power IoT devices-even with pre-quantum public-key cryptography-since IoT devices have tight energy constraints, limited computational power and strict memory limitations. In this paper, we present, to the best of our knowledge, the first in-depth investigation of the application of potential post-quantum key encapsulation mechanisms (KEMs) and digital signature algorithms (DSAs) proposed in the related US NIST process to a state-of-the-art, TLS-based, low-power IoT infrastructure. We implemented these new KEMs and DSAs in such a representative infrastructure and measured their impact on energy consumption, latency and memory requirements during TLS handshakes on an IoT edge device. Based on our investigations, we gained the following new insights. First, we show that the main contributor to high TLS handshake latency is the higher bandwidth requirement of post-quantum primitives rather than the cryptographic computation itself. Second, we demonstrate that a smart combination of multiple DSAs yields the most energy-, latency- and memory-efficient public key infrastructures, in contrast to NIST's goal to standardize only one algorithm. Third, we show that code-based, isogeny-based and lattice-based algorithms can be implemented on a low-power IoT edge device based on an off-the-shelf Cortex M4 microcontroller while maintaining viable battery runtimes. This is contrary to much research that claims dedicated hardware accelerators are mandatory.