Details

Autor(en) / Beteiligte

• Iwashita, Ryoga
• Xu, Zule
• Osada, Masaru
• Iizuka, Tetsuya

Titel

A fractional‐N MASH2‐k FDC phase‐locked loop architecture enabling higher‐order quantisation noise shaping

Ist Teil von

• Electronics letters, 2022-03, Vol.58 (7), p.274-276

Ort / Verlag

Wiley

Erscheinungsjahr

2022

Link zum Volltext

Quelle

Wiley Online Library Journals Frontfile Complete

Beschreibungen/Notizen

• The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability. A MASH2‐k FDC PLL architecture enabling (k + 2)th‐order noise shaping for more flexible loop design optimization and for a wider loop bandwidth to suppress the noise from the digitally controlled oscillator is proposed. The linear loop model is derived, and the noise contributions are analysed. The proposed PLL is evaluated with behavioural simulation whose results are consistent with those of the analysis. The results also suggest a lower phase noise of the proposed PLL compared with the conventional one.