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Rapid prototyping of ASICs with OASIS: An open architecture silicon implementation software
Ist Teil von
SIGDA newsletter, 1991-06, Vol.21 (1), p.77-80
Erscheinungsjahr
1991
Link zum Volltext
Quelle
Alma/SFX Local Collection
Beschreibungen/Notizen
OASIS is a cell-based design system with four major components: the compiler and logic synthesizer, the simulator and verifier, the automatic test pattern generator, and the automatic layout generator. The design flow is top-down as illustrated in the chart below. Currently, the design is captured in LOGIC-III, a PASCAL-like programming language that combines both the functional and structural descriptions. The functional description specifies finite state machines and decoding logic that can be readily synthesized into circuit structures by way of logic synthesis. A scan-path can be inserted automatically in every synthesized component. Data-path circuits are synthesized hierarchically from parameterized structural/functional descriptions of subcomponents. Tools for redundancy identification can be used to detect and to remove any untestable logic.