Details

Autor(en) / Beteiligte

• Oh, Tak-Jun
• Hwang, In-Chul

Titel

A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load

Ist Teil von

• IEEE transactions on very large scale integration (VLSI) systems, 2015-07, Vol.23 (7), p.1281-1286

Ort / Verlag

IEEE

Erscheinungsjahr

2015

Link zum Volltext

• IEEE_Xplore

Quelle

IEL

Beschreibungen/Notizen

• This paper presents a digital low-dropout regulator (D-LDO) with a proposed transient-response boost technique, which enables the reduction of transient response time, as well as overshoot/undershoot, when the load current is abruptly drawn. The proposed D-LDO detects the deviation of the output voltage by overshoot/undershoot, and increases its loop gain, for the time that the deviation is beyond a limit. Once the output voltage is settled again, the loop gain is returned. With the D-LDO fabricated on an 110-nm CMOS technology, we measured its settling time and peak of undershoot, which were reduced by 60% and 72%, respectively, compared with and without the transient-response boost mode. Using the digital logic gates, the chip occupies a small area of 0.04 mm 2 , and it achieves a maximum current efficiency of 99.98%, by consuming the quiescent current of 15 μA at 0.7-V input voltage.