Details

Autor(en) / Beteiligte

• Dabhi, Chetan Kumar
• Rajasekharan, Dinesh
• Pahwa, Girish
• Nandi, Debashish
• Karumuri, Naveen
• Turuvekere, Sreenidhi
• Dutta, Anupam
• Swaminathan, Balaji
• Srihari, Srikanth
• Chauhan, Yogesh S.
• Salahuddin, Sayeef
• Hu, Chenming

Titel

Symmetric BSIM-SOI-Part I: A Compact Model for Dynamically Depleted SOI MOSFETs

Ist Teil von

• IEEE transactions on electron devices, 2024-04, Vol.71 (4), p.2284-2292

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2024

Quelle

IEEE Xplore

Beschreibungen/Notizen

• In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source-drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators, e.g., HSPICE, Spectre, and ADS.