Details

Autor(en) / Beteiligte

• Sreenivasulu, V. Bharath
• Narendar, Vadthiya

Titel

Design Insights of Nanosheet FET and CMOS Circuit Applications at 5-nm Technology Node

Ist Teil von

• IEEE transactions on electron devices, 2022-08, Vol.69 (8), p.4115-4122

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2022

Quelle

IEEE Xplore

Beschreibungen/Notizen

• In this article, FinFET, vertically stacked gate-all-around (GAA) nanowire (NW), and nanosheet (NS) FETs performance are estimated with equal effective channel widths (<inline-formula> <tex-math notation="LaTeX">{W}_{eff} </tex-math></inline-formula>) at the 5-nm technology node (N5). The comparison reveals that NS FET exhibits the highest ON current (<inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle ON}} </tex-math></inline-formula>), the lowest OFF current (<inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula>), and the largest <inline-formula> <tex-math notation="LaTeX">{I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} </tex-math></inline-formula> ratio with better subthreshold performance. We also explore the geometrical variation of the NS FET toward better dc and analog/RF applications and outlined the necessary design guidelines. Moreover, the robustness of NS FET for temperature variations is also performed and analyzed. Finally, the effect of NS width (<inline-formula> <tex-math notation="LaTeX">\text{NS}_{W} </tex-math></inline-formula>) on common source (CS) amplifier, CMOS inverter, and ring oscillator circuits is performed by the Verilog-A model in the CADENCE simulator. An increment of 45.11% in oscillation frequency (<inline-formula> <tex-math notation="LaTeX">f_{osc} </tex-math></inline-formula>), 155.5% rise in CS amplifier gain, <inline-formula> <tex-math notation="LaTeX">2.5\times </tex-math></inline-formula> increment in energy-delay product (EDP), and marginal reduction in inverter noise margin (NM) is noticed with larger <inline-formula> <tex-math notation="LaTeX">\text{NS}_{W} </tex-math></inline-formula>. From the result analysis, it is noticed that for sub-5-nm technological nodes, NS FETs exhibit superior performance and ensure fundamental scaling.