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Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
Ist Teil von
IEEE transactions on electron devices, 2017-10, Vol.64 (10), p.4071-4077
Ort / Verlag
New York: IEEE
Erscheinungsjahr
2017
Quelle
IEEE Xplore
Beschreibungen/Notizen
State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200 mm 2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.