Details

Autor(en) / Beteiligte

• Furber, Steve B.
• Lester, David R.
• Plana, Luis A.
• Garside, Jim D.
• Painkras, Eustace
• Temple, Steve
• Brown, Andrew D.

Titel

Overview of the SpiNNaker System Architecture

Ist Teil von

• IEEE transactions on computers, 2013-12, Vol.62 (12), p.2454-2467

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2013

Quelle

IEEE Xplore

Beschreibungen/Notizen

• SpiNNaker (a contraction of Spiking Neural Network Architecture) is a million-core computing engine whose flagship goal is to be able to simulate the behavior of aggregates of up to a billion neurons in real time. It consists of an array of ARM9 cores, communicating via packets carried by a custom interconnect fabric. The packets are small (40 or 72 bits), and their transmission is brokered entirely by hardware, giving the overall engine an extremely high bisection bandwidth of over 5 billion packets/s. Three of the principal axioms of parallel machine design (memory coherence, synchronicity, and determinism) have been discarded in the design without, surprisingly, compromising the ability to perform meaningful computations. A further attribute of the system is the acknowledgment, from the initial design stages, that the sheer size of the implementation will make component failures an inevitable aspect of day-to-day operation, and fault detection and recovery mechanisms have been built into the system at many levels of abstraction. This paper describes the architecture of the machine and outlines the underlying design philosophy; software and applications are to be described in detail elsewhere, and only introduced in passing here as necessary to illuminate the description.