Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
A delay-locked loop (DLL) circuit is indispensable for clock synchronization in a chip incorporating several heterogeneous dice. It has been shown previously that a fault and soft-error-tolerant DLL can be achieved by triple-module redundancy (TMR) enhanced with a timing correction scheme. However, the prior work still has a severe limitation-it does not consider the latency of the clock tree, and this limitation will make it infeasible in realistic situations. We demonstrate in this article that this limitation can be overcome by a new "clock-latency-aware" architecture, thereby making a fault and soft-error-tolerant DLL truly realistic.