Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
Ergebnis 13 von 2030
IEEE transactions on computer-aided design of integrated circuits and systems, 2019-09, Vol.38 (9), p.1758-1770
2019
Volltextzugriff (PDF)

Details

Autor(en) / Beteiligte
Titel
TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods
Ist Teil von
  • IEEE transactions on computer-aided design of integrated circuits and systems, 2019-09, Vol.38 (9), p.1758-1770
Ort / Verlag
New York: IEEE
Erscheinungsjahr
2019
Quelle
IEEE Xplore
Beschreibungen/Notizen
  • Temperature effect inversion (TEI) phenomenon in ultralow power (ULP) very large scale integration circuits has been identified as an important effect by both academia and industry. Although a number of ULP methods that attempt to exploit the TEI phenomenon have been proposed, the small size of the design exploration space when applying these methods to ULP circuits hinders them from achieving their full potential. This is mainly due to the limited granularity of the supply voltage level control. Starting with an intuition that the body biasing (BB) technique is a key to overcome this limitation, this paper exploits the BB technique along with the TEI-aware voltage scaling (TEI-VS) method and TEI-aware frequency scaling (TEI-FS) method, so as to substantially increase the design spaces of these methods. Techniques for optimally combining the BB technique with TEI-VS and TEI-FS are introduced. Simulation results with the latest commercial CMOS process technologies for ULP designs demonstrate the effectiveness of the proposed methodology.
Sprache
Englisch
Identifikatoren
ISSN: 0278-0070
eISSN: 1937-4151
DOI: 10.1109/TCAD.2018.2859240
Titel-ID: cdi_crossref_primary_10_1109_TCAD_2018_2859240

Weiterführende Literatur

Empfehlungen zum selben Thema automatisch vorgeschlagen von bX