Details

Autor(en) / Beteiligte

• Chih-Wei Chen
• Fayed, Ayman

Titel

A Low-Power Dual-Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS

Ist Teil von

• IEEE journal of solid-state circuits, 2015-09, Vol.50 (9), p.2161-2173

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2015

Quelle

IEEE Xplore

Beschreibungen/Notizen

• The dual-frequency single-inductor multiple-output (DF-SIMO) buck converter topology is proposed. Unlike conventional single-frequency SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency ( ~ 2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A low-power 5-output 2 MHz/120 MHz design in 45 nm with 1.8 V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 V to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10 μH off-chip inductor, 2 nF on-chip capacitor for each 15 mA output and 4.5 nF for the 50 mA output. The peak efficiency is 73%, dynamic voltage scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-regulation transients.