IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.2880-2887
2012
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Details
- Autor(en) / Beteiligte
- Titel
- A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS
- Ist Teil von
- IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.2880-2887
- Ort / Verlag
- New York, NY: IEEE
- Erscheinungsjahr
- 2012
- Quelle
- IEEE Electronic Library Online
- Beschreibungen/Notizen
- A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR with a total of two bits of redundancy. Calibration is leveraged to adjust the uncertain gain of the chosen residue amplifier and various other non-idealities. The ADC achieves a peak SNDR of 62 dB at 10 MS/s, and 56 dB for a Nyquist input at 250 MS/s. The low frequency energy per conversion step ranges from 7 fJ at 10 MS/s to 10 fJ at 250 MS/s.
- Sprache
- Englisch
- Identifikatoren
- ISSN: 0018-9200eISSN: 1558-173XDOI: 10.1109/JSSC.2012.2217873Titel-ID: cdi_crossref_primary_10_1109_JSSC_2012_2217873
- Format
- –
- Schlagworte
- Amplifiers, Analog-digital conversion, analog-digital integrated circuits, Applied sciences, Calibration, Capacitance, Circuit properties, CMOS integrated circuits, CMOS technology, Design. Technologies. Operation analysis. Testing, Electric, optical and optoelectronic circuits, Electronic circuits, Electronics, Exact sciences and technology, Integrated circuits, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Signal convertors, Switches, Transistors