Details

Autor(en) / Beteiligte

• Bulzacchelli, J.F.
• Meghelli, M.
• Rylov, S.V.
• Rhee, W.
• Rylyakov, A.V.
• Ainspan, H.A.
• Parker, B.D.
• Beakes, M.P.
• Aichin Chung
• Beukema, T.J.
• Pepeljugoski, P.K.
• Shan, L.
• Kwark, Y.H.
• Gowda, S.
• Friedman, D.J.

Titel

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

Ist Teil von

• IEEE journal of solid-state circuits, 2006-12, Vol.41 (12), p.2885-2900

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

2006

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization