Details

Autor(en) / Beteiligte

• Mousavikia, Seyed Kian
• Gholizadehazari, Erfan
• Mousazadeh, Morteza
• Yalcin, Siddika Berna Ors

Titel

Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection

Ist Teil von

• IEEE access, 2022, Vol.10, p.58151-58162

Ort / Verlag

Piscataway: IEEE

Erscheinungsjahr

2022

Link zum Volltext

Quelle

EZB Electronic Journals Library

Beschreibungen/Notizen

• This paper describes the design and implementation of a driver drowsiness detection (DDD) system using a modified RiscV processor on a field-programmable gate array (FPGA). To detect drowsiness, Convolutional Neural Network (CNN) is implemented on a RiscV processor. The CNN is trained to classify four primary driver's expressions, including distraction, natural, sleep, and yawn. The trained CNN accuracy is 81.07% on validation data. Furthermore, due to FPGA memory limitations, written C code for the trained CNN is optimized in numerous ways. Optimizations include the usage of dynamic fixed-point data types and dynamic memory allocations. On the other hand, the processor is modified by adding three custom instructions, including custom store, conv2d(<inline-formula> <tex-math notation="LaTeX">2\times 2 </tex-math></inline-formula>), and multiply and accumulation (MAC) to enhance the computation rate. As a result, the processor with custom store, conv2d(<inline-formula> <tex-math notation="LaTeX">2\times 2 </tex-math></inline-formula>), and MAC as custom instructions achieved the best result in terms of latency, with an improvement factor of 1.7 over the base processor and 1.25 over the processor with only custom store and multiply and accumulation (MAC) in exchange of slight increase in area.