Details

Autor(en) / Beteiligte

• Goksel, A.K.
• Krambeck, R.H.
• Thomas, P.P.
• Tsay, M.-S.
• Chen, C.Y.
• Clemons, D.G.
• LaRocca, F.D.
• Mai, L.-P.

Titel

A content addressable memory management unit with on-chip data cache

Ist Teil von

• IEEE journal of solid-state circuits, 1989-06, Vol.24 (3), p.592-596

Ort / Verlag

New York, NY: IEEE

Erscheinungsjahr

1989

Link zum Volltext

• IEEE_Xplore

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T's WE-32200 chip set and is fabricated using a 1 mu m twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set.< >