Details

Autor(en) / Beteiligte

• Chock, C.
• Flood, K.
• Macchiarulo, L.
• Martinez-Mckinney, F.
• Martinez-Rojas, A.
• Mazza, S.
• Mostafanezhad, I.
• Nizam, M.
• Ott, J.
• Perron, R.
• Ryan, E.
• Sadrozinski, H.F.-W.
• Schumm, B.
• Seiden, A.
• Shin, K.
• Tarka, M.
• Uehara, D.
• Wilder, M.
• Zhao, Y.

Titel

First test results of the trans-impedance amplifier stage of the ultra-fast HPSoC ASIC

Ist Teil von

• Journal of instrumentation, 2023-02, Vol.18 (2), p.C02016

Ort / Verlag

Bristol: IOP Publishing

Erscheinungsjahr

2023

Link zum Volltext

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• Abstract We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 μm thick AC-LGAD. The evaluation of the analog front end with β-particles impinging on 3 × 3 AC-LGAD arrays (500 μm pitch, 200 × 200 μm 2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps.