Details

Autor(en) / Beteiligte

• Rahimunnisa, K.
• Karthigaikumar, P.
• Kirubavathy, J.
• Jayakumar, J.
• Kumar, S. Suresh

Titel

A 0.13-µm implementation of 5 Gb/s and 3-mW folded parallel architecture for AES algorithm

Ist Teil von

• International journal of electronics, 2014-02, Vol.101 (2), p.182-193

Ort / Verlag

Taylor & Francis

Erscheinungsjahr

2014

Quelle

Taylor & Francis Journals Auto-Holdings Collection

Beschreibungen/Notizen

• A new architecture for encrypting and decrypting the confidential data using Advanced Encryption Standard algorithm is presented in this article. This structure combines the folded structure with parallel architecture to increase the throughput. The whole architecture achieved high throughput with less power. The proposed architecture is implemented in 0.13-µm Complementary metal-oxide-semiconductor (CMOS) technology. The proposed structure is compared with different existing structures, and from the result it is proved that the proposed structure gives higher throughput and less power compared to existing works.