Details

Autor(en) / Beteiligte

• Zaib, Aurang
• Wild, Thomas
• Herkersdorf, Andreas
• Heisswolf, Jan
• Becker, Jürgen
• Weichslgartner, Andreas
• Teich, Jürgen

Titel

Efficient task spawning for shared memory and message passing in many-core architectures

Ist Teil von

• Journal of systems architecture, 2017-06, Vol.77, p.72-82

Ort / Verlag

Elsevier B.V

Erscheinungsjahr

2017

Quelle

Access via ScienceDirect (Elsevier)

Beschreibungen/Notizen

• Modern many-core systems consist of large number of processing cores and introduce more and more parallelism. The (PGAS) programming model is a popular approach for exploiting this parallelism of architectures while offering flexibility of both shared memory and message passing paradigms. On the architecture design front, (NoCs) have become an integral part of the communication infrastructure due to their good scalability. In order to exploit task level parallelism on modern many-core architectures, the applications spawn more and more tasks to the available computing resources. The applications require less communication and synchronization delays for better performance. However, the distributed nature of NoCs poses a challenge to keep data communication and synchronization latency within the desired bound and hence results in higher task spawning overhead. We proposed an approach based on hardware-assisted task spawning on many-core systems [1]. In the current article, we present an extended version of our work for hardware-managed task spawning, keeping in view the communication requirements of both shared memory and message passing programming models. The proposed hardware support, integrated into the network interface architecture, reduces the synchronization overhead for task spawning. The software is offloaded from task spawning which results in an increase in the overall performance. The simulation results highlight that the proposed task spawning approach improves the overall performance up to 40% in comparison to an existing state-of-the-art approach [2]. To underline the applicability, we implemented an FPGA prototype to investigate real world applications. The investigations show that the proposed concept offers a low overhead in terms of implementation area cost on FPGA and ASIC platforms.