Details

Autor(en) / Beteiligte

• Chae, Hee Jae
• Seok, Ki Hwan
• Lee, Sol Kyu
• Joo, Seung Ki

Titel

Leakage current suppression with a combination of planarized gate and overlap/off-set structure in metal-induced laterally crystallized polycrystalline-silicon thin-film transistors

Ist Teil von

• Solid-state electronics, 2018-04, Vol.142, p.20-24

Ort / Verlag

Elsevier Ltd

Erscheinungsjahr

2018

Quelle

Elsevier ScienceDirect Journals

Beschreibungen/Notizen

• •Inverted staggered MILC poly-Si TFTs with a novel structure have been fabricated.•Planarized gate and overlap/off-set structure was applied to the TFTs.•The TFTs show drastic suppression of leakage current and pinning phenomenon.•The leakage current was decreased by reducing lateral electric field and SCLC leakage current. A novel inverted staggered metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with a combination of a planarized gate and an overlap/off-set at the source-gate/drain-gate structure were fabricated and characterized. While the MILC process is advantageous for fabricating inverted staggered poly-Si TFTs, MILC TFTs reveal higher leakage current than TFTs crystallized by other processes due to their high trap density of Ni contamination. Due to this drawback, the planarized gate and overlap/off-set structure were applied to inverted staggered MILC TFTs. The proposed device shows drastic suppression of leakage current and pinning phenomenon by reducing the lateral electric field and the space-charge limited current from the gate to the drain.