Details

Autor(en) / Beteiligte

• Abiko, Hitoshi
• Ono, Atsuki
• Ueno, Ryuuichi
• Masuoka, Sadaaki
• Shishiguchi, Seiichi
• Nakajima, Ken
• Sakai, Isami

Titel

0.15-μm n-n gate CMOS technology with channel selective epitaxy and transient enhanced diffusion suppression

Ist Teil von

• Electronics & communications in Japan. Part 2, Electronics, 1996, Vol.79 (11), p.28-35

Ort / Verlag

New York: Wiley Subscription Services, Inc., A Wiley Company

Erscheinungsjahr

1996

Quelle

Access via Wiley Online Library

Beschreibungen/Notizen

• An n‐n gate CMOS process with a minimum gate length of 0.15 μm was developed. By means of the epitaxial channel and the transient enhanced diffusion suppression, a shallow buried‐channel layer was realized. It is shown that there is an optimal thickness of the buried‐channel layer that maximizes the drain current, and that the Vt stability is higher in the pMOS in which the channel is fabricated by epitaxy than the conventional pMOS fabricated by channel ion implantation. When the gate poly‐Si and the silicon layer selectively grown on the SD were silicide‐reacted with titanium, a low‐resistance gate electrode with an 0.15‐μm width and the low‐leak SD diffusion layer was realized. From the transistor characteristics obtained in the experiment, the circuit characteristics were simulated. It was found that the delay time of the inverter was 21.5 ps.