Details

Autor(en) / Beteiligte

• Ziegler, Heidi
• Hall, Mary
• Diniz, Pedro

Titel

Compiler-generated communication for pipelined FPGA applications

Ist Teil von

• Annual ACM IEEE Design Automation Conference: Proceedings of the 40th conference on Design automation; 02-06 June 2003, 2003, p.610-615

Ort / Verlag

ACM

Erscheinungsjahr

2003

Link zum Volltext

• Volltext

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targeted for an FPGA with multiple external memories. For this purpose, we extend array data-flow analysis techniques from parallelizing compilers to identify pipeline stages, required inter-pipeline stage communication, and opportunities to find a minimal program execution time by trading communication overhead with the amount of computation overlap in different stages. Using the results of this analysis, we automatically generate application-specific pipelined FPGA hardware designs. We use a sample image processing kernel to illustrate these concepts. Our algorithm finds a solution in which transmitting a row of an array between pipeline stages per communication instance leads to a speedup of 1.76 over an implementation that communicates the entire array at once.