Details

Autor(en) / Beteiligte

• Zolotov, Vladimir
• Visweswariah, Chandu
• Xiong, Jinjun

Titel

Voltage binning under process variation

Ist Teil von

• 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers, 2009, p.425-432

Ort / Verlag

ACM

Erscheinungsjahr

2009

Link zum Volltext

Quelle

ACM Digital Library

Beschreibungen/Notizen

• Process variation is recognized as a major source of parametric yield loss, which occurs because a fraction of manufactured chips do not satisfy timing or power constraints. On the other hand, both chip performance and chip leakage power depend on supply voltage. This dependence can be used for converting the fraction of too slow or too leaky chips into good ones by adjusting their supply voltage. This technique is called voltage binning [4]. All the manufactured chips are divided into groups (bins) and each group is assigned its individual supply voltage. This paper proposes a statistical technique of yield computation for different voltage binning schemes using results of statistical timing and variational power analysis. The paper formulates and solves the problem of computing optimal supply voltages for a given binning scheme.