Details

Autor(en) / Beteiligte

• Pham-Quoc, Cuong
• Heisswolf, Jan
• Werner, Stephan
• Al-Ars, Zaid
• Becker, Jürgen
• Bertels, Koen

Titel

Hybrid interconnect design for heterogeneous hardware accelerators

Ist Teil von

• Proceedings of the Conference on Design, Automation and Test in Europe, 2013, p.843-846

Ort / Verlag

San Jose, CA, USA: EDA Consortium

Erscheinungsjahr

2013

Link zum Volltext

Quelle

IEEE Xplore

Beschreibungen/Notizen

• The communication infrastructure is one of the important components of a multicore system along with the computing cores and memories. A good interconnect design plays a key role in improving the performance of such systems. In this paper, we introduce a hybrid communication infrastructure using both the standard bus and our area-efficient and delay-optimized network on chip for heterogeneous multicore systems, especially hardware accelerator systems. An adaptive data communication-based mapping for reconfigurable hardware accelerators is proposed to obtain a low overhead and latency interconnect. Experimental results show that the proposed communication infrastructure and the adaptive data communication-based mapping achieves a speed-up of 2.4× with respect to a similar system using only a bus as interconnect. Moreover, our proposed system achieves a reduction of energy consumption of 56% compared to the original system.